Many typical graphics processors implement a vertex cache to speed up rendering of indexed primitives. In use, when the same vertex data is used in rendering several primitives, such vertex data need not be separately transformed and lighted for each primitive. Instead, the cached (already transformed and lighted) vertex data may be used. Typically, most vertex caches used in current hardware rely on least-recently-used (LRU) or first-in first-out (FIFO)-type logic. To date, however, there has been no effective attempt to further optimize the use of vertex caches.
There is thus a need for addressing these and/or other issues associated with the prior art.